The CDCV850 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the 2-line serial interface (SDATA,SCLK), and the analog power input (AVDD). A two-line serial interface can put the individual output clock pairs in a high-impedance state. When the AVDD terminal is tied to GND, the PLL is turned off and bypassed for test purposes.

The device provides a standard mode (100 Kbits/s) 2-line serial interface for device control. The implementation is as a slave/receiver. The device address is specified in the 2-line serial device address table. Both of the 2-line serial inputs (SDATA and SCLK) provide integrated pullup resistors (typically 100 kΩ).

Two 8-bit, 2-line serial registers provide individual enable control for each output pair. All outputs default to enabled at powerup. Each output pair can be placed in a high-impedance mode, when a low-level control bit is written to the control register. The registers must be accessed in sequential order (i.e., random access of the registers not supported). The serial interface circuit can be supplied with either 2.5 V or 3.3 V (at VDDI) in applications where this programming option is not required (after power up, all output pairs will then be enabled).

When the input frequency falls below a suggested detection frequency that is below 20 MHz (typically 10 MHz), the output pairs are put into a high-impedance condition, the PLL is shut down, and the device will enter a low power mode. The CDCV850 is also able to track spread spectrum clocking for reduced EMI.

Since the CDCV850 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up, as well as changes to various 2-line serial registers that affect the PLL. The CDCV850 is characterized in a temperature range from –40°C to 85°C.

• Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
• Spread Spectrum Clock Compatible
• Operating Frequency: 60 to 140 MHz
• Low Jitter (cyc.cyc): ±75 ps
• Distributes One Differential Clock Input to Ten Differential Outputs
• Two-Line Serial Interface Provides Output Enable and Functional Control
• Outputs Are Put Into a High-Impedance State When the Input Differential Clocks Are <20 MHz
• 48-Pin TSSOP Package
• Consumes <250-µA Quiescent Current
• External Feedback Pins (FBIN, FBIN) Are Used to Synchronize the Outputs to the Input Clocks