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DS90UR124 - 产品图解:
DS90UR124-5-43MHz DC 平衡 24 位 FPD 链接 II 解串器
DS90UR124-FPD-LinkII串行器/解串器-显示和成像串行器/解串器-接口
DS90UR124-DS90URxxx-Q1 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset
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TI产品 - DS90UR124介绍
DS90UR124 - 5-43MHz DC 平衡 24 位 FPD 链接 II 解串器

DS90UR124是TI公司的一款FPD-LinkII串行器/解串器产品,DS90UR124是5-43MHz DC 平衡 24 位 FPD 链接 II 解串器,本页介绍了DS90UR124的产品说明、应用、特性等,并给出了与DS90UR124相关的TI元器件型号供参考。

DS90UR124 - 5-43MHz DC 平衡 24 位 FPD 链接 II 解串器 - FPD-LinkII串行器/解串器 - 显示和成像串行器/解串器 - TI公司(Texas Instruments,德州仪器)

产品特性
  • Supports Displays With 18-Bit Color Depth
  • 5-MHz to 43-MHz Pixel Clock
  • Automotive-Grade Product AEC-Q100 Grade 2 Qualified
  • 24:1 Interface Compression
  • Embedded Clock With DC Balancing Supports AC-Coupled Data Transmission
  • Capable to Drive up to 10 Meters Shielded Twisted-Pair Cable
  • No Reference Clock Required (Deserializer)
  • Meets ISO 10605 ESD – Greater than 8 kV HBM ESD Structure
  • Hot Plug Support
  • EMI Reduction – Serializer Accepts Spread Spectrum Input; Data Randomization and Shuffling on Serial Link; Deserializer Provides Adjustable PTO (Progressive Turnon) LVCMOS Outputs
  • @Speed BIST (Built-In Self-Test) to Validate LVDS Transmission Path
  • Individual Power-Down Controls for Both Transmitter and Receiver
  • Power Supply Range 3.3 V ±10%
  • 48-Pin TQFP Package for Transmitter and 64-Pin TQFP Package for Receiver
  • Temperature Range: –40°C to 105°C
  • Backward-Compatible Mode With DS90C241/DS90C124
产品应用
  • Automotive Central Information Displays
  • Automotive Instrument Cluster Displays
  • Automotive Heads-Up Displays
  • Remote Camera-Based Driver Assistance Systems
产品说明

The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is ideally suited for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional general-purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range, EMI is further reduced.

产品器件信息
PART NUMBERPACKAGEBODY SIZE (NOM)
DS90UR124-Q1TQFP (64)10.00 mm × 10.00 mm
DS90UR241-Q1TQFP (48)7.00 mm × 7.00 mm
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