The SLK2511C is a single chip multirate transceiver IC used to derive high-speed timing signals forSONET/SDH based equipment. The chip performs clock and data recovery, serial-to-parallel/parallel-to-serial conversion and frame detection function conforming to the SONET/SDH standards.

The device can be configured to operate under OC-48, OC-24, OC-12, or OC-3 data rates through the rate selection pins or the autorate detection function. An external reference clock operating at 155.52 MHz or 622.08 MHz is required for the recovery loop, and it also provides a stable clock source in the absence of serial data transitions.

The SLK2511C accepts 4-bit LVDS parallel data/clock and generates a NRZ SONET/SDH-compliant signal at OC-3, OC-12, OC-24, or OC-48 rates. It also recovers the data and clock from the serial SONET stream and demultiplexes it into 4-bit LVDS parallel data for full duplex operation. TXDATA0 and RXDATA0 are the first bits that are transmitted and received in time, respectively. The serial interface is a low jitter, PECL compatible differential interface.

The SLK2511C provides a comprehensive suite of built-in tests for self-test purposes including local and remote loopback and PRBS (27-1) generation and verification.

The device comes in a 100-pin VQFP package that requires a single 2.5-V supply with 3.3-V tolerant inputs on the control pins. The SLK2511C is power efficient, dissipating less than 900 mW at 2.488 Gbps, the OC-48 data rate, and it is characterized for operation from -40°C to 85°C.

• Fully Integrated SONET/SDH Transceiver toSupport Clock/Data Recovery and Multiplexer/Demultiplexer Functions
• Supports OC-48, OC-24, OC-12, Gigabit Ethernet, and OC-3 Data Rate With Autorate Detection
• Supports Transmit Only, Receiver Only, Transceiver and Repeater Functions in a Single Chip Through Configuration Pins
• Supports SONET/SDH Frame Detection
• On-Chip PRBS Generation and Verification
• Supports 4-Bit LVDS (OIF99.102) Electrical Interface
• Parity Checking and Generation for the LVDS Interface
• Single 2.5-V Power Supply
• Interfaces to Back Plane, Copper Cables, or Optical Modules
• Hot Plug Protection
• Low Jitter PECL Compatible Differential Serial Interface With Programmable De-Emphasis for the Serial Output
• On-Chip Termination for LVDS and PECL Compatible Interface
• Receiver Differential Input Thresholds 150 mV Min
• Supports SONET Loop Timing
• Low Power CMOS
• ESD Protection >2 kV
• 155-MHz or 622-MHz Reference Clock
• Maintains Clock Output in Absence of Data
• Local and Remote Loopback
• 100-Pin PZP Package With PowerPAD Design With 5-mm × 5-mm (Typ) Heatsink