TI,TI公司,TI代理商
TI(德州仪器)| TI产品型号搜索
专营TI元器件,强大的现货交付能力,解决您的采购难题
全流程提供TI现货供应链服务
当前位置:TI公司 > > TI芯片 >> SN54ABT7819
SN54ABT7819技术文档下载:
SN54ABT7819技术文档产品手册下载
SN54ABT7819 - 产品图解:
http://www.ti.com/cn/lit/gpn/sn54abt7819
承诺原装正品
专营TI,真正优化您的供应链
TI产品 - SN54ABT7819介绍
SN54ABT7819 - 512 x 18 x 2 同步双向 FIFO 存储器

SN54ABT7819是TI公司的一款FIFO寄存器产品,SN54ABT7819是512 x 18 x 2 同步双向 FIFO 存储器,本页介绍了SN54ABT7819的产品说明、应用、特性等,并给出了与SN54ABT7819相关的TI元器件型号供参考。

SN54ABT7819 - 512 x 18 x 2 同步双向 FIFO 存储器 - FIFO寄存器 - 触发器/锁存器/寄存器 - TI公司(Texas Instruments,德州仪器)

产品描述

A FIFO memory is a storage device that allows data to be read from its array in the same order it is written. The SN54ABT7819 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. Two independent 512 × 18 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions, a half-full flag, and a programmable almost-full/almost-empty flag.

The SN54ABT7819 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

The state of the A0-A17 outputs is controlled by CSA\ and W/R\A. When both CSA\ and W/R\A are low, the outputs are active. The A0-A17 outputs are in the high-impedance state when either CSA\ or W/R\A is high. Data is written to FIFOA-B from port A on the low-to-high transition of CLKA when CSA\ is low, W/R\A is high, WENA is high, and the IRA flag is high. Data is read from FIFOB-A to the A0-A17 outputs on the low-to-high transition of CLKA when CSA\ is low, W/R\A is low, RENA is high, and the ORA flag is high.

The state of the B0-B17 outputs is controlled by CSB\ and W/R\B. When both CSB\ and W/R\B are low, the outputs are active. The B0-B17 outputs are in the high-impedance state when either CSB\ or W/R\B is high. Data is written to FIFOB-A from port B on the low-to-high transition of CLKB when CSB\ is low, W/R\B is high, WENB is high, and the IRB flag is high. Data is read from FIFOA-B to the B0-B17 outputs on the low-to-high transition of CLKB when CSB\ is low, W/R\B is low, RENB is high, and the ORB flag is high.

The setup- and hold-time constraints for the chip selects (CSA\, CSB\) and write/read selects (W/R\A, W/R\B) enable and read operations on memory and are not related to the high-impedance control of the data outputs. If a port read enable (RENA or RENB) and write enable (WENA or WENB) are set low during a clock cycle, the chip select and write/read select can switch at any time during the cycle to change the state of the data outputs.

The input-ready and output-ready flags of a FIFO are two-stage synchronized to the port clocks for use as reliable control signals. CLKA synchronizes the status of the input-ready flag of FIFOA-B (IRA) and the output-ready flag of FIFOB-A (ORA). CLKB synchronizes the status of the input-ready flag of FIFOB-A (IRB) and the output-ready flag of FIFOA-B (ORB). When the input-ready flag of a port is low, the FIFO receiving input from the port is full and writes are disabled to its array. When the output-ready flag of a port is low, the FIFO that outputs data to the port is empty and reads from its memory are disabled. The first word loaded to an empty memory is sent to the FIFO output register at the same time its output-ready flag is asserted (high). When the memory is read empty and the output-ready flag is forced low, the last valid data remains on the FIFO outputs until the output-ready flag is asserted (high) again. In this way, a high on the output-ready flag indicates new data is present on the FIFO outputs.

The SN54ABT7819 is characterized for operation over the full military temperature range of -55°C to 125°C.

产品特性

  • Member of the Texas Instruments WidebusTM Family
  • Advanced BiCMOS Technology
  • Free-Running CLKA and CLKB Can Be Asynchronous or Coincident
  • Read and Write Operations Synchronized to Independent System Clocks
  • Two Separate 512 × 18 Clocked FIFOs Buffering Data in Opposite Directions
  • IRA and ORA Synchronized to CLKA
  • IRB and ORB Synchronized to CLKB
  • Microprocessor Interface Control Logic
  • Programmable Almost-Full/Almost-Empty Flag
  • Fast Access Times of 9 ns With a 50-pF Load and Simultaneous-Switching Data Outputs
  • Released as DSCC SMD (Standard Microcircuit Drawing) 5962-9470401QXA and 5962-9470401QYA
  • Package Options Include 84-Pin Ceramic Pin Grid Array (GB) and 84-Pin Ceramic Quad Flat (HT) Package

Widebus is a trademark of Texas Instruments Incorporated.

下面可能是您感兴趣的TI公司FIFO寄存器元器件
  • UCC28501 - BiCMOS PFC/PWM 组合控制器
  • TPS65162 - 具有输入到输出集成隔离开关、2 个运算放大器和 GPM 的 4 通道 LCD 偏置
  • DRV8825 - 具有片上 1/32 微步进分度器的 2.5A 双极步进电机驱动器(Step/Dir 控制器)
  • LM5134 - 具有备用导频输出的单个 7.6A 峰值电流低侧栅极驱动器
  • TPS3808G18 - 低静态电流可编程延迟监控电路
  • TPA0212 - 具有立体声耳机驱动和集成增益的立体声 AB 类音频放大器
  • DLPC3438 - 低功耗 DLP 显示控制器
  • LMX2502 - Frequency Synthesizer System with Integrated VCOs
  • RF430FRL154H - RF430FRL15xH NFC ISO15693 传感器应答器
  • TPS22942 - 5.5V,0.2A,400mΩ,100mA 限流低电平有效负载开关
  • 节约时间成本,提高采购效率,TI官网授权代理
    TI公司|TI德州仪器|德州仪器TI公司代理商|TI芯片代理商
    TI公司产品现货专家,订购TI公司产品不限最低起订量,TI产品大陆现货即时发货,香港库存3-5天发货,海外库存7-10天发货
    寻找全球TI代理商现货货源 - TI公司(德州仪器)电子元件在线订购