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SN65DSI86 - 产品图解:
SN65DSI86-MIPI? DSI 桥至 eDP
SN65DSI86-CSI/DSI-显示和成像串行器/解串器-接口
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TI产品 - SN65DSI86介绍
SN65DSI86 - MIPI? DSI 桥至 eDP

SN65DSI86是TI公司的一款CSI/DSI产品,SN65DSI86是MIPI? DSI 桥至 eDP,本页介绍了SN65DSI86的产品说明、应用、特性等,并给出了与SN65DSI86相关的TI元器件型号供参考。

SN65DSI86 - MIPI? DSI 桥至 eDP - CSI/DSI - 显示和成像串行器/解串器 - TI公司(Texas Instruments,德州仪器)

产品特性
  • Embedded DisplayPort™ (eDP™) 1.4 Compliant Supporting 1, 2, or 4 Lanes at 1.62 Gbps (RBR), 2.16 Gbps, 2.43 Gbps, 2.7 Gbps (HBR), 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps (HBR2).
  • Implements MIPI® D-PHY Version 1.1 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00
  • Dual-Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1.5 Gbps Per Lane
  • Supports 18 bpp and 24 bpp DSI Video Packets With RGB666 and RGB888 Formats
  • Suitable for 60 fps 4K 4096 × 2304 Resolution at 18 bpp Color, and WUXGA 1920 × 1200 Resolution with 3D Graphics at 60 fps (120 fps Equivalent)
  • MIPI Front-End Configurable for Single-Channel or Dual-Channel DSI Configuration
  • Supports Dual-Channel DSI Odd, Even and Left, Right Operating Modes
  • 1.2-V Main VCC Power Supply and 1.8-V Supply for Digital I/Os
  • Low-Power Features Include Panel Refresh and MIPI Ultralow Power State (ULPS) Support
  • DisplayPort Lane Polarity and Assignment Configurable.
  • Supports 12-MHz, 19.2-MHz, 26-MHz, 27-MHz, and 38.4-MHz Frequencies Through External Reference Clock (REFCLK)
  • Adaptive Content Management and Backlight PWM Control Enabling Optimal User Viewing Experience in Both Low and Bright Ambient Light Environments Available in SN65DSI96.
  • ESD Rating ±4 kV (HBM)
  • Packaged in 64-Pin 5-mm x 5-mm MicroStar Junior BGA (ZQE)
  • Temperature Range: –40°C to +85°C
产品应用
  • Tablet PCs, Notebook PCs, Netbooks
  • Mobile Internet Devices
产品说明

The SN65DSI86 and SN65DSI96 (SN65DSIx6) DSI to embedded DisplayPort (eDP) bridge features a dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1.5 Gbps per lane and a maximum input bandwidth of 12 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a DisplayPort with up to four lanes at either 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps.

The SN65DSIx6 is well suited for WQXGA at 60 frames per second, as well as 3D graphics at 4K and true HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and DisplayPort interfaces.

产品器件信息
PART NUMBERPACKAGEBODY SIZE (NOM)
SN65DSI86BGA MicroStar Junior (64)5.00 mm × 5.00 mm
SN65DSI96
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