SN65LVDS117是TI公司的一款LVDSPHY(<800Mbps)产品,SN65LVDS117是双路 8 端口 LVDS 中继器,本页介绍了SN65LVDS117的产品说明、应用、特性等,并给出了与SN65LVDS117相关的TI元器件型号供参考。
SN65LVDS117 - 双路 8 端口 LVDS 中继器 - LVDSPHY(<800Mbps) - LVDS/M-LVDS/ECL/CML - TI公司(Texas Instruments,德州仪器)
The SN65LVDS109 and SN65LVDS117 are configured as two identical banks, each bank having one differential line receiver connected to either four ('109) or eight ('117) differential line drivers. The outputs are arranged in pairs having one output from each of the two banks. Individual output enables are provided for each pair of outputs and an additional enable is provided for all outputs.
The line receivers and line drivers implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise emission, high noise immunity, and high switching speeds. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)
The intended application of these devices, and the LVDS signaling technique, is for point-to-point or point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same silicon substrate, along with the low pulse skew of balanced signaling, provides extremely precise timing alignment of the signals being repeated from the inputs. This is particularly advantageous for implementing system clock and data distribution trees.
The SN65LVDS109 and SN65LVDS117 are characterized for operation from –40°C to 85°C.
- Two Line Receivers and Eight ('109) or Sixteen ('117) Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
- Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz
- Outputs Arranged in Pairs From Each Bank
- Enabling Logic Allows Individual Control of Each Driver Output Pair, Plus All Outputs
- Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100- Load
- Electrically Compatible With LVDS, PECL, LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT, SSTL, or HSTL Outputs With External Termination Networks
- Propagation Delay Times < 4.5 ns
- Output Skew Less Than 550 psBank Skew Less Than150 ps Part-to-Part Skew Less Than 1.5 ns
- Total Power Dissipation Typically <500 mW With All Ports Enabled and at 200 MHz
- Driver Outputs or Receiver Input Equals High Impedance When Disabled or With
下面可能是您感兴趣的TI公司LVDSPHY(<800Mbps)元器件
- BQ25010 - 单片锂离子充电器和 DC/DC 转换器 IC,输出可调节
- SN65LVEP11 - PECL/ECL 1:2 扇出缓冲器
- LP3985 - 微功耗,150mA 低噪声超低压降 CMOS 电压稳压器
- TL7709A - 具有可编程时间延迟的单路 SVS,用于 9V 系统
- OPA1654 - Sound Plus 低噪声和低失真通用 FET 输入音频运算放大器
- LM2842-Q1 - 采用超薄 SOT-23 封装的 600 mA 最高 42V 输入降压 DC/DC 稳压器
- LP38692-ADJ - 1A Low Dropout CMOS Linear Regulators with Adjustable Output Stable with Ceramic Output Capacitors
- CY74FCT2574T - 具有三态输出和串联阻尼电阻的八路 D 类寄存器
- SN74F573 - 具有三态输出的八路透明 D 类锁存器
- TPS51461 - 具有 2 位 VID 的 3.3V 至 5V 输入、6A、D-CAP+ 模式同步降压转换器