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SN74ALVCH16823 - 产品图解:
SN74ALVCH16823-具有三态输出的 18 位总线接口触发器
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TI产品 - SN74ALVCH16823介绍
SN74ALVCH16823 - 具有三态输出的 18 位总线接口触发器

SN74ALVCH16823是TI公司的一款D类触发器产品,SN74ALVCH16823是具有三态输出的 18 位总线接口触发器,本页介绍了SN74ALVCH16823的产品说明、应用、特性等,并给出了与SN74ALVCH16823相关的TI元器件型号供参考。

SN74ALVCH16823 - 具有三态输出的 18 位总线接口触发器 - D类触发器 - 触发器/锁存器/寄存器 - TI公司(Texas Instruments,德州仪器)

产品描述

This 18-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16823 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The SN74ALVCH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, thus latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently of the clock.

A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

The output-enable (OE) input does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16823 is characterized for operation from -40°C to 85°C.

产品特性

  • Member of the Texas Instruments Widebus™ Family
  • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

Widebus, EPIC are trademarks of Texas Instruments.

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