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SN74LVC1G373 - 产品图解:
SN74LVC1G373-具有三态输出的单路 D 类锁存器
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TI产品 - SN74LVC1G373介绍
SN74LVC1G373 - 具有三态输出的单路 D 类锁存器

SN74LVC1G373是TI公司的一款无产品,SN74LVC1G373是具有三态输出的单路 D 类锁存器,本页介绍了SN74LVC1G373的产品说明、应用、特性等,并给出了与SN74LVC1G373相关的TI元器件型号供参考。

SN74LVC1G373 - 具有三态输出的单路 D 类锁存器 - 无 - 小尺寸逻辑器件 - TI公司(Texas Instruments,德州仪器)

产品描述

This single D-type latch is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

While the latch-enable (LE) input is high, the Q output follows the data (D) input. When LE is taken low, the Q output is latched at the logic level set up at the D input.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

OE does not affect the internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

产品特性

  • Available in the Texas Instruments NanoFree Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Provides Down Translation to VCC
  • Max tpd of 4 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

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