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SN75ALS176B - 产品图解:
SN75ALS176B-差动总线收发器
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TI产品 - SN75ALS176B介绍
SN75ALS176B - 差动总线收发器

SN75ALS176B是TI公司的一款无产品,SN75ALS176B是差动总线收发器,本页介绍了SN75ALS176B的产品说明、应用、特性等,并给出了与SN75ALS176B相关的TI元器件型号供参考。

SN75ALS176B - 差动总线收发器 - 无 - RS-485收发器 - TI公司(Texas Instruments,德州仪器)

产品描述

The SN65ALS176 and SN75ALS176 series differential bus transceivers are designed for bidirectional data communication on multipoint bus transmission lines. They are designed for balanced transmission lines and meet TIA/EIA-422-B, TIA/EIA-485-A, and ITU Recommendations V.11 and X.27.

The SN65ALS176 and SN75ALS176 series combine a 3-state, differential line driver and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, that can be connected together externally to function as a direction control. The driver differential outputs and the receiver differential inputs are connected internally to form a differential input/output (I/O) bus port that is designed to offer minimum loading to the bus when the driver is disabled or VCC = 0. This port features wide positive and negative common-mode voltage ranges, making the device suitable for party-line applications.

The SN65ALS176 is characterized for operation from -40°C to 85°C. The SN75ALS176 series is characterized for operation from 0°C to 70°C.

产品特性

  • Meet or Exceed the Requirements of TIA/EIA-422-B, TIA/EIA-485-A and ITU Recommendations V.11 and X.27
  • Operate at Data Rates up to 35 Mbaud
  • Four Skew Limits Available:
  • SN65ALS176...15 ns
  • SN75ALS176...10 ns
  • SN75ALS176A...7.5 ns
  • SN75ALS176B...5 ns
  • Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments
  • Low Supply-Current Requirements ...30 mA Max
  • Wide Positive and Negative Input/Output Bus-Voltage Ranges
  • Thermal Shutdown Protection
  • Driver Positive and Negative Current Limiting
  • Receiver Input Hysteresis
  • Glitch-Free Power-Up and Power-Down Protection
  • Receiver Open-Circuit Fail-Safe Design

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