The TLK2218 is the third generation of Gigabit Ethernet transceivers from Texas Instruments combining high port density and ultra-low power in a small form-factor footprint. The TLK2218 provides for high-speed full-duplex point-to-point data transmissions based on the IEEE 802.3z 1000-Mbps Ethernet specification. The TLK2218 supports data rates from 1.0 Gbps through 1.3 Gbps in full rate mode, or 0.5 Gbps through 0.65 GbPs in half rate mode.

The primary application of this device is to provide building blocks for developing point-to-point baseband data transmission over controlled impedance media of 50?. The transmission media can be printed circuit board traces, copper cables or fiber-optical interface modules. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The TLK2218 performs the data encoding, decoding, serialization, deserialization, clock extraction and clock tolerance compensation functions for a physical layer interface device. Each channel operates at up to 1.3Gbps providing up to 8.32Gbps of aggregate data bandwidth over copper or optical-media interfaces.

The TLK2218 supports two selectable reduced-pin-count double-data-rate (DDR) timing interfaces, nibble mode and multiplexed channel mode, to a protocol device.

In the nibble interface mode, the parallel interface accepts nibble-wide unencoded or 8b/10b encoded data aligned to both the rising and falling edges of the transmit clock.

In the multiplexed channel mode, the parallel interface accepts 8-bit-wide unencoded or 10-bit-wide 8b/10b encoded data with channels A, C, E, and G aligned to the falling edge of the source synchronous transmit clock and channels B, D, F, and H aligned to the rising edge of the transmit clock. The receive path interface is done in the same manner.

The TLK2218 aligns the recovered data clock frequency to the reference clock on each channel by means of a clock tolerance compensation circuit and internal FIFO that inserts or drops 20-bit IDLE codes as needed in the interpacket gap (IPG). In synchronous mode, the received data for all channels is aligned to a single receive data clock that is a buffered version of the reference clock.

The TLK2218 supports a selectable IEEE 802.3z compliant 8b/10b encoder/decoder in all its modes of operation.

The TLK2218 automatically locks onto incoming data without the need to pre-lock.

The TLK2218 provides a comprehensive series of built-in tests for self-test purposes including loopback and PRBS generation and verification. An IEEE 1149.1 JTAG port is also supported to aid in board-manufacturing testing.

The TLK2218 is housed in a small form-factor 19×19-mm, 289-terminal BGA with 1,0-mm ball pitch.

The TLK2218 is characterized to support the commercial temperature range of 0°C to 70°C.

The TLK2218 consumes 1.3 W when operating at nominal conditions.

The TLK2218 is designed to be hot-plug capable. A power-on reset puts the serial side output signal terminals TX+/TX- in the high-impedance state during power up.

• Eight 1.0- to 1.3-Gigabits Per Second (Gbps) Synchronizable Transceivers
• Haft-Rate Operation (0.5 to 0.65 Gbps)
• Low Power Consumption <1.3 W Typical at 1.25 Gbps
• IEEE 802.3z Gigabit Ethernet Compliant
• Differential VML Transmit Outputs With No External Components Necessary. PECL Compatible Levels
• Programmable High-Speed Output Preemphasis Levels
• Selectable Parallel Interface Modes:
  • Nibble-Wide Double Data Rate (DDR) Clocking Interface
  • Multiplexed Channel DDR Clock Interface
• Selectable Clock Tolerance Compensation
• Selectable On-Chip 8b/10b IEEE 802.3z Compliant Encoder and Decoder
• JEDEC-Compliant 1.8-V LVCMOS (Extendable to 2.5 V)
• 3.6-V Tolerant Inputs on Parallel I/O
• Internal Series Termination on LVCMOS Outputs to Drive 50- Lines
• Source Centered Timing on Parallel Inputs and Outputs
• Comprehensive Suite of Built-In Testability Features (PRBS Generation and Verification, Serial Loopback, and Far-End Loopback)
• IEEE 802.3 Clause 22 Management Data Interface (MDIO) Support
• IEEE 1149.1 JTAG Support
• Hot-Plug Protection on Serial I/O
• No External Filter Components Required for PLLs
• Small Footprint 19×19-mm, 289-Terminal, 1,0-mm Ball-Pitch BGA
• Advanced Low-Power 0.18-μm CMOS Technology
• Commercial Temperature Rating (0°C to 70°C)
• APPLICATIONS
  • Point-to-Point Baseband Data Transmission