The TLK3101 is a member of the transceiver family of multigigabit transceivers, intended for use in ultrahigh-speed bidirectional point-to-point data transmission systems. The TLK3101 supports an effective serial interface speed of 2.5 Gbps to 3.125 Gbps providing up to 2.5 Gbps of data bandwidth. The TLK3101 is functionally identical to the TLK1501, a 0.6 Gbps to 1.5 Gbps transceiver, and the TLK2501, a 1.6 Gbps to 2.5 Gbps transceiver, providing a wide range of performance solutions with no significant board layout changes. NOTE: The TLK3101 does have an integrated termination resistance unlike the TLK2501 and TLK1501.

The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband data transmission over controlled impedance media of approximately 50 . The transmission media can be printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

This device can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector pins, and transmit/receive pins. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance backplane, or an optical link. It is then reconstructed into its original parallel format. It offers significant power and cost savings over current solutions, as well as scalability for a higher data rate in the future.

The TLK3101 performs the data parallel-to-serial, serial-to-parallel conversion, and clock extraction functions for a physical layer interface device. The serial transceiver interface operates at a maximum speed of 3.125 Gbps. The transmitter latches 16-bit parallel data at a rate based on the supplied reference clock (GTX_CLK). The 16-bit parallel data is internally encoded into 20 bits using an 8-bit/10-bit encoding format. The resulting 20-bit word is then transmitted differentially at 20 times the reference clock (GTX_CLK) rate. The receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data to the extracted reference clock (RX_CLK). It then decodes the 20 bit wide data using 8-bit/10-bit decoding format resulting in 16 bits of parallel data at the receive data pins (RXD0-15). This results in an effective data payload of 2 Gbps to 2.5 Gbps (16 bits data x GTX_CLK frequency).

The TLK3101 is housed in a high-performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is recommended that the TLK3101 PowerPAD be soldered to the thermal land on the board. All ac performance specifications in this data sheet are measured with the PowerPAD soldered to the test board.

The TLK3101 provides an internal loopback capability for self-test purposes. Serial data from the serializer is passed directly to the deserializer allowing the protocol device a functional self-check of the physical interface.

The TLK3101 is designed to be hot plug capable. An on-chip power-on reset circuit holds the RX_CLK low during power up. Also, this circuit holds the parallel side output signal terminals as well as DOUTTXP and DOUTTXN in a high-impedance state.

The TLK3101 has a loss of signal detection circuit for conditions where the incoming signal no longer has a sufficient voltage amplitude to keep the clock recovery circuit in lock.

To prevent a data bit error from causing a valid data packet to be interpreted as a comma and thus causing the erroneous word alignment by the comma detection circuit, the comma word alignment circuit is turned off after the link is properly established in the TLK3101.

The TLK3101 allows users to implement redundant ports by connecting receive data bus terminals from two TLK3101 devices together. Asserting LCKREFN to a low state will cause the receive data bus pins, RXD[0:15], RX_CLK, and RX_ER, RX_DV/LOS to go to a high-impedance state. This places the device in a transmit only mode since the receiver is not tracking the data.

The TLK3101 uses a 2.5-V supply. The I/O section is 3 V compatible. With the 2.5-V supply the chipset is very power efficient, consuming less than 450 mW typically. The TLK3101 is characterized for operation from –40°C to 85°C.

• Hot-Plug Protection
• 2.5 Gigabits to 3.125 Gigabits Per Second (Gbps) Serializer/Deserializer
• High Performance 64-Pin VQFP Thermally Enhanced Package (PowerPAD™)
• 2.5-V Power Supply for Low Power Operation
• PECL Compatible Differential Signalling Serial Interface
• Interfaces to Backplane, Copper Cables, or Optical Converters
• On-Chip 8-Bit/10-Bit Encoding/Decoding, Comma Alignment and Link Synchronization
• On-Chip PLL Provides Clock Synthesis From Low-Speed Reference
• Receiver Differential Input Thresholds 200 mV Min
• Typical Power . . . 450 mW
• Loss of Signal (LOS) Detection
• Ideal for High-Speed Backplane Interconnect and Point-to-Point Data Link

PowerPAD is a trademark of Texas Instruments.