The TLK4015 is a four-channel multigigabit transceiver used in ultrahigh-speed bidirectional point-to-point data transmission systems. The four channels in the TLK4015 are configured as four separate links. The TLK4015 supports an effective serial interface speed of 0.6 Gbps to 1.5 Gbps per channel, providing up to 1.2 Gbps of data bandwidth per channel.

The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband data transmission over controlled-impedance media of approximately 50 . The transmission media can be printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling from the environment.

This device can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector terminals, and transmit/receive terminals. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel. It is then reconstructed into its original parallel format. It offers significant power and cost savings over current solutions, as well as scalability for higher data rates in the future.

The TLK4015 performs parallel-to-serial and serial-to-parallel data conversion. The clock extraction functions as a physical layer interface device. The serial transceiver interface operates at a maximum speed of 1.5 Gbps. Each transmitter latches 16-bit parallel data at a rate based on the supplied reference clock (GTx_CLK). The 16-bit parallel data is internally encoded into 20 bits using an 8-bit/10-bit (8b/10b) encoding format. The resulting 20-bit word is then transmitted differentially at 20 times the reference clock (GTx_CLK) rate. The receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data to the extracted reference clock (Rx_CLK). It then decodes the 20-bit-wide data using 8-bit/10-bit decoding format, resulting in 16 bits of parallel data at the receive data terminals RDx[0–15]). The outcome is an effective data payload of 480 Mbps to 1.2 Gbps (16 bits data × the GTx_CLK frequency) per channel.

The TLK4015 provides an internal loopback capability for self-test purposes. Serial data from the serializer is passed directly to the deserializer, allowing the protocol device a functional self-check of the physical interface.

The TLK4015 is designed to be hot-plug capable. An on-chip power-on reset circuit holds the Rx_CLK low during power up. This circuit also holds the parallel side output signal terminals as well as DOUTTxP and DOUTTxN in a high-impedance state during power up.

The TLK4015 has a loss-of-signal detection circuit for conditions where the incoming signal no longer has sufficient voltage amplitude to keep the clock recovery circuit in lock.

To prevent a data bit error from causing a valid data packet to be interpreted as a comma and thus causing erroneous word alignment by the comma detection circuit, the comma word alignment circuit is turned off after the link is properly established in TLK4015.

The TLK4015 allows users to implement redundant ports by connecting receive data bus pins from two TLK4015 devices together. Asserting LCKREFNx to a low state drives the receive data bus pins, RDx[0–15], Rx_CLK and Rx_ER, Rx_DV/LOSx to a high-impedance state. This places the device in a transmit-only mode because the receiver is not tracking the data.

The TLK4015 uses a 2.5-V supply. The I/O section is 3-V compatible. With the 2.5-V supply the device is very power-efficient, typically consuming less than 1.5 W. The TLK4015 is characterized for operation from –40°C to 85°C.

• Hot Plug Protection
• Quad 0.6 to 1.5 Gigabits Per Second (Gbps) Serializer/Deserializer
• Independent Channel Operation
• 2.5-V Power Supply for Low-Power Operation
• Programmable Voltage Output Swing on Serial Output
• Interfaces to Backplane, Copper Cables, or Optical Converters
• Rated for Industrial Temperature Range
• On-Chip 8-Bit/10-Bit (8b/10b) Encoding/Decoding, Comma Alignment, and Link Synchronization
• On-Chip PLL Provides Clock Synthesis From Low-Speed Reference
• Receiver Differential Input Thresholds 200 mV Minimum
• Typical Power: 1 W
• Loss-of-Signal (LOS) Detection
• Ideal for High-Speed Backplane Interconnect and Point-to-Point Data Link
• Small Footprint 19×19-mm 289-Ball PBGA Package