The iceLynx-Micro (consumer electronics link with integrated microcontroller and physical layer (PHY)) is a high performance 1394 link-layer device designed as a total solution for digitally interfacing advanced audio/video consumer electronics applications. The device is offered in both a DTCP encryption/decryption version (TSB43CA43A and TSB43CA42) and a non-DTCP encryption/decryption version (TSB43CB43).

In addition to supporting transmit and receive of MPEG2 and DSS formatted transport streams with encryption and decryption, iceLynx-Micro supports the IEC 61883-6 and audio music protocol standards for audio format and packetizing, and asynchronous and asynchronous stream (as defined by 1394).

The device also features an embedded ARM7TDMI microprocessor core with access to 256K bytes of internal program memory. The ARM7 is embedded to process 1394 specific transactions, thus significantly reducing the processing power required by the host CPU and the development time required by the user. The ARM7 is accessed from the 16/1-bit host CPU interface, from a UART communication port, or from a JTAG debug port.

The iceLynx-Micro integrated 3-port PHY allows the user enhanced flexibility as two additional devices can be utilized in a system application. The PHY’s speeds are capable of running at 100 Mbps, 200 Mbps, or 400 Mbps. The PHY follows all requirements as stated in the IEEE 1394-1995 and IEEE 1394a-2000 standards.

The TSB43CA43A and TSB43CA42 version of iceLynx-Micro incorporates two M6 baseline ciphers (one per HSDI port) per the 5C specification to support transmit and receive of MPEG2 formatted transport streams with encryption and decryption. The TSB43CB43 version of iceLynx-Micro is identical to the TSB43CA43A without implementation of the encryption/decryption features. The TSB43CB43 device allows customers that do not require the encryption/decryption features to incorporate iceLynx-Micro without becoming DTLA licensees. Both devices support the IEC 61883-6 and audio music protocol standards for audio format and packetizing.

• 1394 Features
  • Integrated 400 Mbps 3-port PHY
  • Compliant with IEEE 1394-1995 and IEEE 1394a-2000 standards
  • Supports bus manager functions and automatic 1394 self-ID verification.
  • Separate Async Ack FIFO decreases the ack-tracking burden on in-CPU and ex-CPU
• DTLA Encryption Support for MPEG2-DVB, DSS, DV, and Audio (TSB43CA43A and TSB43CA42 Only)
  • Two M6 baseline ciphers (one per HSDI port)
    • Content key generation from exchange key
  • AKE acceleration features in hardware
    • Random Number Generator
    • Secure Hash Algorithm, Revision 1 (SHA-1)
  • Other AKE acceleration features
    • Elliptical curve digital signature algorithm (EC-DCA) both signature and verification
    • Elliptical curve Diffie-Hellman (EC-DH), first phase value and shared secret calculation
    • 160-bit math functions
• High Speed Data Interface (HSDI)
  • Two configurable high speed data interfaces support the following audio and video modes:
    • MPEG2-DVB interface
    • MPEG2-DSS interface
    • DV codec interface
    • IEC60958 interface
    • Audio DAC interface
    • SACD interface
• External CPU Interface
  • 16-bit parallel asynchronous I/O-type
  • 16-bit parallel synchronous I/O-type
  • 16-bit parallel synchronous memory type
• Internal ARM7
  • 50-MHz operating frequency
  • 32-bit and thumb (16-bit) mode support
  • UART included for communication
  • 256K bytes of program memory included on chip
  • ARM JTAG included for software debug
• Data Buffers
  • Large 16.5K byte total FIFO
  • Programmable data/space available indicators for buffer flow control
• Hardware Packet Formatting for the Following Standards
  • DVB MPEG2 transport stream (IEC61883-4)
  • DSS MPEG2 transport stream per standard
  • DV Stream (IEC 61883-2) SD-DV
  • Audio over 1394 (IEC 61883-6)
  • Audio Music Protocol (version 1.0 and enhancements)
  • Asynchronous and asynchronous stream (as defined by IEEE 1394)
• Additional Features
  • PID filtering for transmit function (up to 16 separate PIDs per HSDI)
  • Packet insertion – two insertion buffers per HSDI
  • 11 general-purpose inputs/outputs (GPIOs)
  • Interrupt driven to minimize CPU polling.
  • Single 3.3-V supply
  • JTAG interface to support post-assembly scan of device I/O – boundary scan