The TSB43Ex42/43 is high-performance consumer electronics IEEE 1394 link layer and integrated physical layer devices designed for digitally interfacing advanced video consumer electronics applications. It supports formatting and transmission of IEC61883 data, including IEC61883-1 (general), IEC61883-2 (SD-DVCR), IEC61883-4 (MPEG2-TS), and IEC61883-7 (ITU-R BO.1294 SystemB-DSS). The TSB43Ex42/43 also supports standard IEEE 1394 data types, such as asynchronous, asynchronous streams, and PHY packets.

The TSB43EAxx/ECxx version incorporates DTCP (M6) baseline per the DTLA (5C) specification to support transmit and receive of up to two MPEG2 transport streams with encryption and decryption. The TSB43EAxx/ECxx version also includes hardware acceleration for content key generation.

The TSB43EBxx series are identical to the TSB43EAxx/ECxx series without implementation of the encryption/decryption features. The TSB43EB42/43 devices allow customers that do not require the encryption/decryption features to incorporate the TSB43Ex42/43 function without becoming DTLA licensees.

The TSB43Ex42/43 features an integrated 2-port/3-port PHY. The PHY operates at 100 Mbps, 200 Mbps, or 400 Mbps. They follow all requirements as stated in the IEEE 1394-1995 and IEEE 1394a-2000 standards.

Designing with this device may require extensive support. Before incorporating this device into a design, customers should contact TI or an Authorized TI Distributor.

• IEEE 1394 Features
  • Integrated 400/200/100-Mbps 2-Port/3-Port PHY
  • Compliant to IEEE Std 1394-1995 and IEEEStd1394a-2000
  • Supports Bus Manager Functions and Automatic 1394 Self-ID Verification
  • Separate Asynchronous ACK Buffers Decrease ACK-Tracking Burden on External CPU
• DTCP and AES Encryption Support for MPEG-DVB and DSS (TSB43EA42/43 and TSB43EC42/43 Only)
  • DTCP Encryption Support on IEEE Std 1394 Bus
  • AES128 Encryption Support on HSDI Path (TSB43EC42/43 Only)
  • Support for up to Two Encrypted/Decrypted Streams at One Time
  • Full or Restricted AKE Performed With Hardware Assist
  • Secure Loading of DTCP and AES128 Information Using External CPU Interface
  • Localization Support Compliant With DTCP Draft Revision 1.51
• Video Interfaces
  • Two Configurable High-Speed Data Ports for Video Data
    • One Port Configurable As Parallel Or Serial
    • One Port Serial Only
  • Pass-Through Modes for HSDI0 and HSDI1
  • Packet Insertion – Two Insertion Buffers per HSDI for PAT, PMT, SIT, and DIT Packets
  • PID Filtering (32 PID Filters per HSDI Port)
• External CPU Interfaces
  • Motorola 68K-Style 16-Bit Asynchronous Interface
  • SRAM-Like 16-Bit Asynchronous Interface
  • PCI Interface (33 MHz) Compliant to PCI Specification Version 3.0 (Supports PCI Slave and Master Function)
• DMA
  • Higher Asynchronous Throughput With DMA Hardware Enhancements (Available in PCI Mode Only)
  • Internal DMA Controller – Asynchronous, Asynchronous Stream TX/RX
    • General DMA
    • Auto Response DMA for SBP2 Transactions
• Data Buffers
  • 2 × 4K-Byte Isochronous Buffers for Video Data
  • 2 × 2K-Byte Asynchronous/Asynchronous Stream Transmit Buffers
  • 2 × 2K-Byte Asynchronous/Asynchronous Stream Receive Buffers
  • 1 × 1K-Byte Self-ID Buffer
  • Insertion Buffers for MPEG-DVB/DSS Packet Insertion
  • Programmable Data/Space Available Indicators for Buffer Flow Control
• Hardware Packet Formatting Standards
  • IEC61883-1 (General)
  • IEC61883-2 (SD-DVCR)
  • IEC61883-4 (MPEG2-TS)
  • IEC61883-7 (ITU-R BO.1294 System B) – DSS
  • Generic 61883 Mode
  • Asynchronous Packets
  • Asynchronous Streams
  • PHY Packets (Including Self-IDs)
  • MPEG4 Supported Under IEC61883-4 (No New Requirement for MPEG4 Over IEEEStd1394)
• Additional Features
  • JTAG Interface to Support Post-Assembly Scan of Device I/O – Boundary Scan
  • Unique "Binding" Method Protects Sensitive Data on the Circuit Board Traces at the External CPU Interface
  • Unique "EMI-AES Binding" Method Prevents Protected Data From Being Transmitted in the Clear